EP2A25F672I8 vs EP2A25F672C9 Comparison
Detailed side-by-side comparison of EP2A25F672I8 by Altera and EP2A25F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672I8 | EP2A25F672C9 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | APEX II | APEX II |
| Logic Elements / Cells | 24,320 | — |
| Equivalent Gates | 900,000 | — |
| Embedded Memory (RAM bits) | 622,592 | — |
| User I/Os | 492 | — |
| Number of PLLs | 4 | — |
| Process Technology | 0.15 µm CMOS, up to 8 metal layers | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Supply Voltage | 1.5 V | — |
| Propagation Delay | 1.69 ns (typical) | 1.69 ns |
| Internal Performance | 333 MHz (per legacy datasheet) | — |
| LVDS / High-Speed I/O | Yes, up to 1 Gbps | — |
| Package | 672-ball FC-FBGA (FineLine BGA), 27 × 27 mm, 1 mm pitch | 672-ball FCBGA (FineLine BGA) |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| Operating Temperature | –40 °C to +85 °C (industrial, 'I' grade) | 0°C to 85°C (Commercial) |
| Speed Grade | I8 (industrial, 8-speed-grade per APEX II ordering scheme) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, GTL+, PCI | — |
| RoHS Status | unknown | [DATA_NEEDED] |
| Lead-Free Status | unknown | — |
| Logic Elements (LE) | — | Approximately 25,000 |
| Macro Cells | — | 2432 |
| User I/O | — | 492 |
| Package Dimensions | — | 27 mm x 27 mm |
| Ball Pitch | — | 1.0 mm |
| Logic Family | — | CMOS |
| Supply Voltage | — | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | — | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | — | Passive Serial, Passive Parallel Synchronous, JTAG |
| Embedded Memory | — | ESBs for dual-port RAM, ROM, FIFO |