EP2A25F672I8 vs EP2A25F672C9 तुलना
विस्तृत दोनों ओर की तुलना EP2A25F672I8 द्वारा Altera और EP2A25F672C9 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP2A25F672I8 | EP2A25F672C9 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | NRND |
| Family | APEX II | APEX II |
| Logic Elements / Cells | 24,320 | — |
| Equivalent Gates | 900,000 | — |
| Embedded Memory (RAM bits) | 622,592 | — |
| User I/Os | 492 | — |
| Number of PLLs | 4 | — |
| Process Technology | 0.15 µm CMOS, up to 8 metal layers | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Supply Voltage | 1.5 V | — |
| Propagation Delay | 1.69 ns (typical) | 1.69 ns |
| Internal Performance | 333 MHz (per legacy datasheet) | — |
| LVDS / High-Speed I/O | Yes, up to 1 Gbps | — |
| पैकेज | 672-ball FC-FBGA (FineLine BGA), 27 × 27 mm, 1 mm pitch | 672-ball FCBGA (FineLine BGA) |
| माउंटिंग प्रकार | Surface Mount (BGA) | Surface Mount |
| ऑपरेटिंग तापमान | –40 °C to +85 °C (industrial, 'I' grade) | 0°C to 85°C (Commercial) |
| Speed Grade | I8 (industrial, 8-speed-grade per APEX II ordering scheme) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, GTL+, PCI | — |
| RoHS स्थिति | unknown | [DATA_NEEDED] |
| Lead-Free Status | unknown | — |
| Logic Elements (LE) | — | Approximately 25,000 |
| Macro Cells | — | 2432 |
| User I/O | — | 492 |
| Package Dimensions | — | 27 mm x 27 mm |
| Ball Pitch | — | 1.0 mm |
| Logic Family | — | CMOS |
| सप्लाई वोल्टेज | — | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | — | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | — | Passive Serial, Passive Parallel Synchronous, JTAG |
| Embedded Memory | — | ESBs for dual-port RAM, ROM, FIFO |