EP2A40F672C9 vs EP2A40F672C9ES Comparison
Detailed side-by-side comparison of EP2A40F672C9 by Altera and EP2A40F672C9ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera
EP2A40F672C9 β Last Time Buy
Specification Comparison
| Parameter | EP2A40F672C9 | EP2A40F672C9ES |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $62.00 | $195.00 |
| Family | APEX II | APEX II |
| Device Family | APEX II PLD | β |
| Logic Elements / Cells | 38,400 | β |
| System Gates | 1.5 M | 1,500,000 |
| Macros | 2,560 | β |
| User I/Os | 492 | β |
| Number of Pins | 672 | β |
| Package | 672-BBGA, FC-FBGA (FineLine) | 672-pin FC-FBGA |
| Package Size | 27 mm Γ 27 mm, 1 mm ball pitch | β |
| Core Voltage | 1.5 V | 1.5 V |
| Process Technology | 0.15 Β΅m all-layer copper, up to 8 metal layers | 0.15 Β΅m CMOS |
| Logic Family | CMOS | β |
| Propagation Delay | 1.55 ns | β |
| Internal Speed Grade | 366 MHz | β |
| Operating Temperature | 0 Β°C to 85 Β°C (commercial) | β |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Logic Elements | β | 38,400 |
| Maximum User I/O | β | 492 |
| Operating Frequency (max) | β | 366 MHz |
| Speed Grade | β | -9 |
| Configuration Modes | β | PS, PPS, PPA, JTAG, FPP |
| Embedded Memory (ESB) | β | Yes (RAM/ROM/CAM) |
| I/O Standards | β | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |