EP2A40F672C9 vs EP2A40F672C9ES 比較
詳細並排比較 EP2A40F672C9 由 Altera 與 EP2A40F672C9ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A40F672C9 | EP2A40F672C9ES |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | NRND |
| Family | APEX II | APEX II |
| Device Family | APEX II PLD | — |
| Logic Elements / Cells | 38,400 | — |
| System Gates | 1.5 M | 1,500,000 |
| Macros | 2,560 | — |
| User I/Os | 492 | — |
| 腳位數 | 672 | — |
| 封裝 | 672-BBGA, FC-FBGA (FineLine) | 672-pin FC-FBGA |
| Package Size | 27 mm × 27 mm, 1 mm ball pitch | — |
| Core Voltage | 1.5 V | 1.5 V |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.15 µm CMOS |
| Logic Family | CMOS | — |
| Propagation Delay | 1.55 ns | — |
| Internal Speed Grade | 366 MHz | — |
| 工作溫度 | 0 °C to 85 °C (commercial) | — |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport | — |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| Logic Elements | — | 38,400 |
| Maximum User I/O | — | 492 |
| Operating Frequency (max) | — | 366 MHz |
| Speed Grade | — | -9 |
| Configuration Modes | — | PS, PPS, PPA, JTAG, FPP |
| Embedded Memory (ESB) | — | Yes (RAM/ROM/CAM) |
| I/O Standards | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |