EP2A40F672C9ES vs EP2A40F672C9 Comparison
Detailed side-by-side comparison of EP2A40F672C9ES by Altera and EP2A40F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera
EP2A40F672C9 β Last Time BuySpecification Comparison
| Parameter | EP2A40F672C9ES | EP2A40F672C9 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $62.00 |
| Family | APEX II | APEX II |
| Logic Elements | 38,400 | β |
| System Gates | 1,500,000 | 1.5 M |
| Maximum User I/O | 492 | β |
| Operating Frequency (max) | 366 MHz | β |
| Process Technology | 0.15 Β΅m CMOS | 0.15 Β΅m all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V | 1.5 V |
| Package | 672-pin FC-FBGA | 672-BBGA, FC-FBGA (FineLine) |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| Speed Grade | -9 | β |
| Configuration Modes | PS, PPS, PPA, JTAG, FPP | β |
| Embedded Memory (ESB) | Yes (RAM/ROM/CAM) | β |
| I/O Standards | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ | β |
| Boundary Scan | IEEE 1149.1 (JTAG) | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| Device Family | β | APEX II PLD |
| Logic Elements / Cells | β | 38,400 |
| Macros | β | 2,560 |
| User I/Os | β | 492 |
| Number of Pins | β | 672 |
| Package Size | β | 27 mm Γ 27 mm, 1 mm ball pitch |
| Logic Family | β | CMOS |
| Propagation Delay | β | 1.55 ns |
| Internal Speed Grade | β | 366 MHz |
| Operating Temperature | β | 0 Β°C to 85 Β°C (commercial) |
| I/O Standards Supported | β | True-LVDS, LVPECL, PCML, HyperTransport |