EP2S60F1020C5N vs EP2S60F1020I4 Comparison
Detailed side-by-side comparison of EP2S60F1020C5N by Altera and EP2S60F1020I4 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2S60F1020C5N | EP2S60F1020I4 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $143.75 | $1,454.92 |
| Series | Stratix II | Stratix II |
| Number of Logic Elements | 60440 | β |
| Number of LABs/CLBs | 3022 | 3022 |
| Number of Logic Array Blocks | 3022 LABs | β |
| Total RAM Bits | 2544192 bits | β |
| Number of User I/O | 718 | β |
| Package / Case | 1020-BBGA, FCBGA | β |
| Number of Terminals | 1020 | β |
| Terminal Form | BALL | β |
| Package Code | BGA | β |
| Package Shape | SQUARE | β |
| Supply Voltage | 1.15 V to 1.25 V | β |
| Operating Temperature | 0Β°C ~ 85Β°C (TJ) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Speed Grade / Order Code | C5 (commercial speed grade per Altera order code) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (contains lead per legacy Altera package) |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL] | β |
| Number of DSP Blocks | [DATA_NEEDED: Number of DSP blocks] | β |
| Number of M512 RAM Blocks | [DATA_NEEDED: Number of M512 RAM blocks] | β |
| Number of M4K RAM Blocks | [DATA_NEEDED: Number of M4K RAM blocks] | β |
| Manufacturer | β | Intel / Altera |
| Logic Elements (LEs) | β | 60,440 |
| Embedded Memory (bits) | β | 2,544,192 |
| Number of CLBs | β | 24176 |
| Maximum User I/O | β | 718 |
| Number of I/O Banks | β | [DATA_NEEDED: number of I/O banks] |
| Operating Voltage (Core) | β | 1.2 V |
| Process Technology | β | 90 nm CMOS |
| Temperature Grade | β | Industrial (-40C to +100C TJ) |
| Package Type | β | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Package Dimensions | β | 33 mm x 33 mm |
| Ball Pitch | β | 1.0 mm |
| Configuration Method | β | Passive Serial / Fast Passive Parallel / JTAG |
| Number of PLLs | β | 12 |
| Global Clock Networks | β | 16 |
| Embedded Multipliers (18x18) | β | 36 |
| Transceiver Count | β | 0 (no embedded transceivers) |
| Maximum Embedded Memory Bandwidth | β | [DATA_NEEDED: memory bandwidth spec] |