EP2S60F67214N vs EP2S30F672I4 Comparison
Detailed side-by-side comparison of EP2S60F67214N by Altera and EP2S30F672I4 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2S60F67214N | EP2S30F672I4 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Stratix II | — |
| Logic Elements | 60,440 LE | 33880 |
| Total RAM Bits | 2,544,192 bit (2.5 Mbit) | 1369728 |
| DSP Blocks | 12 | 12 (per datasheet, family range) |
| Phase-Locked Loops (PLLs) | 4 | — |
| Package | 672-ball FBGA (FineLine BGA) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Speed Grade | I4 (industrial, fast) | — |
| Operating Temperature | -40C to +100C (industrial) | -40C to +100C (Industrial) |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V (typical) | — |
| I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for FBGA-672] | — |
| Configuration | SRAM-based, configured via bitstream | JTAG, serial, parallel (Stratix II scheme) |
| RoHS Status | Lead-free / RoHS compliant | [DATA_NEEDED: confirm RoHS compliance on part label] |
| MSL Level | 3 (168 hours floor life) | 3 (per JEDEC J-STD-020) |
| Series | — | Stratix II |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Array Blocks (LABs) | — | 1694 |
| Number of I/O | — | 500 |
| Number of PLLs | — | 6 |
| Voltage - Supply | — | 1.2 V core, separate I/O bank VCCIO |
| Package / Case | — | 672-BBGA, FCBGA (FBGA-672) |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.0 mm |