EP2S60F67214N vs EP2S30F672I4 Vergleich
Detaillierter Direktvergleich von EP2S60F67214N von Altera und EP2S30F672I4 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2S60F67214N | EP2S30F672I4 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $232,00 | $695,00 |
| Family | Stratix II | — |
| Logic Elements | 60,440 LE | 33880 |
| Total RAM Bits | 2,544,192 bit (2.5 Mbit) | 1369728 |
| DSP Blocks | 12 | 12 (per datasheet, family range) |
| Phase-Locked Loops (PLLs) | 4 | — |
| Gehäuse | 672-ball FBGA (FineLine BGA) | — |
| Montageart | Surface Mount | Surface Mount |
| Speed Grade | I4 (industrial, fast) | — |
| Betriebstemperatur | -40C to +100C (industrial) | -40C to +100C (Industrial) |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V (typical) | — |
| I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for FBGA-672] | — |
| Configuration | SRAM-based, configured via bitstream | JTAG, serial, parallel (Stratix II scheme) |
| RoHS-Status | Lead-free / RoHS compliant | [DATA_NEEDED: confirm RoHS compliance on part label] |
| MSL-Level | 3 (168 hours floor life) | 3 (per JEDEC J-STD-020) |
| Series | — | Stratix II |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Array Blocks (LABs) | — | 1694 |
| Number of I/O | — | 500 |
| Number of PLLs | — | 6 |
| Voltage - Supply | — | 1.2 V core, separate I/O bank VCCIO |
| Gehäuse / Bauform | — | 672-BBGA, FCBGA (FBGA-672) |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.0 mm |