EP2SGX60FF1152 vs EP2SGX60EF1152I4N Comparison

Detailed side-by-side comparison of EP2SGX60FF1152 by Altera and EP2SGX60EF1152I4N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP2SGX60FF1152 EP2SGX60FF1152 - Stratix II GX FPGA 60K LE 1152-BGA | Altera

EP2SGX60FF1152 - Stratix II GX FPGA 60K LE 1152-BGA | Altera

EP2SGX60FF1152 ⚠ Last Time Buy
Intel
EP2SGX60EF1152I4N EP2SGX60EF1152I4N - 60,440-LCell FPGA, 717 MHz | Intel

EP2SGX60EF1152I4N - 60,440-LCell FPGA, 717 MHz | Intel

EP2SGX60EF1152I4N βœ“ Active

Specification Comparison

Parameter EP2SGX60FF1152 EP2SGX60EF1152I4N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Active
Stock Status In Stock In Stock
Unit Price (USD) $1,950.00 $0.00
Series Stratix II GX β€”
Family Stratix II GX FPGA β€”
Logic Elements 60,440 β€”
Embedded Memory 2,544,192 bits 2,544,192 bits
DSP Blocks (18x18 Multipliers) 192 (16 blocks) β€”
Maximum User I/O 364 β€”
Number of LABs/CLBs 3022 β€”
Transceivers 12 channels up to 3.125 Gbps β€”
Package 1152-BBGA, FineLine BGA (FF1152) 1,152-ball FBGA
Operating Temperature -40C to +85C (industrial) β€”
Voltage - Supply 1.2 V core / multiple VCCIO rails β€”
Mounting Type Surface Mount Surface mount
Process Technology 90 nm CMOS, SRAM-based β€”
Configuration Method JTAG IEEE 1149.1, Serial, Passive Parallel, Fast Passive Parallel β€”
RoHS Status Compliant β€”
Device Type β€” FPGA
Product Family β€” Stratix II GX
Logic Cells β€” 60,440
I/O Count β€” 534
Internal Frequency β€” 717 MHz
Supply Voltage β€” 1.2 V
Package Type β€” Other, 23 x 23 mm, 1 mm pitch, MS-034AAJ-1, FBGA-484
Pins β€” 484
Device Technology β€” 90 nm
Logic Blocks β€” 3,022 LABs
Operating Temperature Grade β€” Industrial
Compliance β€” [DATA_NEEDED: compliance certification details]
Transceiver Count β€” [DATA_NEEDED: high-speed transceiver count]
Configuration Memory β€” [DATA_NEEDED: configuration memory specification]
Package Pinout β€” [DATA_NEEDED: complete ball-map pinout]

Datasheets & Resources

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