EP610DC-10 vs EP610ILC-10 Comparison
Detailed side-by-side comparison of EP610DC-10 by Intel and EP610ILC-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-10 | EP610ILC-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 16 | 16 |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | — |
| Speed Grade | -10 | — |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | PLCC-28 (plastic J-lead chip carrier) |
| Mounting Type | Through-Hole | Surface Mount (PLCC socket or solder) |
| Technology | CMOS, EPROM-based (UV-erasable) | — |
| Supply Voltage | 5 V (single supply) | 5 V (single supply) |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 16 |
| Logic Elements | 16 macrocells (programmable AND/OR array) | — |
| Configuration Memory | UV-erasable EPROM | — |
| Reprogrammable | Yes (UV erase window on package) | — |
| RoHS Status | [DATA_NEEDED: not stated in verified web data] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | UV-Erasable / OTP PLD |
| Architecture | — | PAL-type with macrocells |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |