EP610DC-10 vs EP610ILC-10 Comparaison
Comparaison détaillée côte à côte de EP610DC-10 par Intel et EP610ILC-10 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610DC-10 | EP610ILC-10 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,95 | $7,20 |
| Device Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 16 | 16 |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | — |
| Speed Grade | -10 | — |
| Boîtier | 24-pin CDIP (Ceramic DIP, windowed) | PLCC-28 (plastic J-lead chip carrier) |
| Type de montage | Through-Hole | Surface Mount (PLCC socket or solder) |
| Technology | CMOS, EPROM-based (UV-erasable) | — |
| Tension d'alimentation | 5 V (single supply) | 5 V (single supply) |
| Température de fonctionnement | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 16 |
| Logic Elements | 16 macrocells (programmable AND/OR array) | — |
| Configuration Memory | UV-erasable EPROM | — |
| Reprogrammable | Yes (UV erase window on package) | — |
| Statut RoHS | [DATA_NEEDED: not stated in verified web data] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | UV-Erasable / OTP PLD |
| Architecture | — | PAL-type with macrocells |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |