EP610DC-15 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610DC-15 by Altera and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610DC-15 | EP610DC-25 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $9.95 |
| Product Family | Classic EPLD (EP610) | β |
| Architecture | UV-erasable CMOS PAL-type | β |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | β |
| Dedicated Inputs | 20 | β |
| Bidirectional I/O Pins | 16 | β |
| Total Product Terms | 160 | β |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | β |
| Maximum Internal Clock Frequency | 71.4 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0C to 70C (commercial) | 0 C to +70 C |
| Package | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (Ceramic DIP, through-hole) |
| Mounting Type | Through-Hole | Through Hole |
| Programming Method | JEDEC fuse map, UV erasure | JEDEC fuse-map / UV-erase |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Family | β | Altera Classic EPLD |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | β | 300 |
| Maximum Propagation Delay (tPD) | β | 25 ns |
| Pipelined Data Rate | β | Up to 100 MHz |
| Number of I/O Pins | β | 22 |
| Number of Dedicated Inputs | β | 4 |
| Total Pin Count | β | 24 |
| Speed Grade Suffix | β | -25 (25 ns tPD) |