EP610DC-15 vs EP610DC-25 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610DC-15 disebabkan oleh Altera dan EP610DC-25 disebabkan oleh Rochester Electronics. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP610DC-15 EP610DC-25
Merek Altera Rochester Electronics
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Aktif
Product Family Classic EPLD (EP610) —
Architecture UV-erasable CMOS PAL-type —
Macrocells 16 16
Logic Expanders 4 —
Dedicated Inputs 20 —
Bidirectional I/O Pins 16 —
Total Product Terms 160 —
Propagation Delay (tPD) 15 ns (speed grade -15) —
Maximum Internal Clock Frequency 71.4 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V 4.75 V to 5.25 V (5 V nominal)
Suhu Operasi 0C to 70C (commercial) 0 C to +70 C
Kemasan 24-pin Ceramic DIP (CDIP-24) with UV window 24-pin CDIP (Ceramic DIP, through-hole)
Jenis Pemasangan Through-Hole Through Hole
Programming Method JEDEC fuse map, UV erasure JEDEC fuse-map / UV-erase
Technology CMOS CMOS EPROM (UV-erasable)
Status RoHS [DATA_NEEDED: RoHS status] —
Family — Altera Classic EPLD
Product Type — EPLD (Erasable Programmable Logic Device)
Equivalent Gates — 300
Maximum Propagation Delay (tPD) — 25 ns
Pipelined Data Rate — Up to 100 MHz
Number of I/O Pins — 22
Number of Dedicated Inputs — 4
Total Pin Count — 24
Speed Grade Suffix — -25 (25 ns tPD)

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