EP610DC-15 vs EP610DC-25 비교
다음의 상세 나란히 비교: EP610DC-15 제조: Altera 및 EP610DC-25 제조: Rochester Electronics. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ 활성사양 비교
| 파라미터 | EP610DC-15 | EP610DC-25 |
|---|---|---|
| 브랜드 | Altera | Rochester Electronics |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $7.95 | $9.95 |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | — |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| 동작 온도 | 0C to 70C (commercial) | 0 C to +70 C |
| 패키지 | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (Ceramic DIP, through-hole) |
| 실장 유형 | Through-Hole | Through Hole |
| Programming Method | JEDEC fuse map, UV erasure | JEDEC fuse-map / UV-erase |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | — |
| Family | — | Altera Classic EPLD |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Speed Grade Suffix | — | -25 (25 ns tPD) |