EP610DC-15 vs EP610IDC-10 Comparison
Detailed side-by-side comparison of EP610DC-15 by Altera and EP610IDC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-15 | EP610IDC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $8.85 |
| Product Family | Classic EPLD (EP610) | β |
| Architecture | UV-erasable CMOS PAL-type | β |
| Macrocells | 16 | β |
| Logic Expanders | 4 | β |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | β |
| Total Product Terms | 160 | β |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | β |
| Maximum Internal Clock Frequency | 71.4 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (nominal) |
| Operating Temperature | 0C to 70C (commercial) | β |
| Package | 24-pin Ceramic DIP (CDIP-24) with UV window | β |
| Mounting Type | Through-Hole | Through-hole |
| Programming Method | JEDEC fuse map, UV erasure | β |
| Technology | CMOS | CMOS, UV-erasable (windowed ceramic) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CDIP-10 variant] |
| Device Family | β | Altera Classic EPLD |
| Logic Capacity | β | 300 usable gates |
| Macrocell Count | β | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | β | 10 ns |
| Maximum Counter Frequency (fCNT) | β | 100 MHz |
| I/O Logic Compatibility | β | 100% TTL emulation |
| Package Type | β | 24-pin Ceramic DIP (CDIP) |
| I/O Pins | β | 20 |
| Operating Temperature Range | β | 0 Β°C to +70 Β°C (commercial) |
| Programmable Interconnect | β | Yes (on-chip) |
| In-System Programmability | β | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | β | Yes (per device documentation) |