EP610DC-15 vs EP610IDC-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-15 sa pamamagitan ng Altera at EP610IDC-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-15 | EP610IDC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | — |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | — |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (nominal) |
| Temperature na Operasyon | 0C to 70C (commercial) | — |
| Packhaging | 24-pin Ceramic DIP (CDIP-24) with UV window | — |
| Uri ng Pagpapasok | Through-Hole | Through-hole |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | CMOS, UV-erasable (windowed ceramic) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CDIP-10 variant] |
| Device Family | — | Altera Classic EPLD |
| Logic Capacity | — | 300 usable gates |
| Macrocell Count | — | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | — | 10 ns |
| Maximum Counter Frequency (fCNT) | — | 100 MHz |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Package Type | — | 24-pin Ceramic DIP (CDIP) |
| I/O Pins | — | 20 |
| Hanay ng Temperature na Operasyon | — | 0 °C to +70 °C (commercial) |
| Programmable Interconnect | — | Yes (on-chip) |
| In-System Programmability | — | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | — | Yes (per device documentation) |