EP610DC-15 vs EP610IDC-10 对比
详细并排对比 EP610DC-15 出自 Altera 和 EP610IDC-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610DC-15 | EP610IDC-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $7.95 | $8.85 |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | — |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | — |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (nominal) |
| 工作温度 | 0C to 70C (commercial) | — |
| 封装 | 24-pin Ceramic DIP (CDIP-24) with UV window | — |
| 安装类型 | Through-Hole | Through-hole |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | CMOS, UV-erasable (windowed ceramic) |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CDIP-10 variant] |
| Device Family | — | Altera Classic EPLD |
| Logic Capacity | — | 300 usable gates |
| Macrocell Count | — | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | — | 10 ns |
| Maximum Counter Frequency (fCNT) | — | 100 MHz |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Package Type | — | 24-pin Ceramic DIP (CDIP) |
| I/O Pins | — | 20 |
| 工作温度范围 | — | 0 °C to +70 °C (commercial) |
| Programmable Interconnect | — | Yes (on-chip) |
| In-System Programmability | — | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | — | Yes (per device documentation) |