EP610DC-25 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610DC-25 by Rochester Electronics and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610DC-25 | EP610DC-15 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $7.95 |
| Family | Altera Classic EPLD | β |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | β |
| Maximum Propagation Delay (tPD) | 25 ns | β |
| Pipelined Data Rate | Up to 100 MHz | β |
| Number of I/O Pins | 22 | β |
| Number of Dedicated Inputs | 4 | β |
| Total Pin Count | 24 | β |
| Package | 24-pin CDIP (Ceramic DIP, through-hole) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Mounting Type | Through Hole | Through-Hole |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Operating Temperature | 0 C to +70 C | 0C to 70C (commercial) |
| Technology | CMOS EPROM (UV-erasable) | CMOS |
| Programming Method | JEDEC fuse-map / UV-erase | JEDEC fuse map, UV erasure |
| Speed Grade Suffix | -25 (25 ns tPD) | β |
| Product Family | β | Classic EPLD (EP610) |
| Architecture | β | UV-erasable CMOS PAL-type |
| Logic Expanders | β | 4 |
| Dedicated Inputs | β | 20 |
| Bidirectional I/O Pins | β | 16 |
| Total Product Terms | β | 160 |
| Propagation Delay (tPD) | β | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | β | 71.4 MHz |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |