EP610DC-25 vs EP610DC-15 比較
詳細並排比較 EP610DC-25 由 Rochester Electronics 與 EP610DC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ 啟用中規格比較
| 參數 | EP610DC-25 | EP610DC-15 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | Obsolete |
| Family | Altera Classic EPLD | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | — |
| Maximum Propagation Delay (tPD) | 25 ns | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Number of I/O Pins | 22 | — |
| Number of Dedicated Inputs | 4 | — |
| Total Pin Count | 24 | — |
| 封裝 | 24-pin CDIP (Ceramic DIP, through-hole) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 安裝類型 | Through Hole | Through-Hole |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| 工作溫度 | 0 C to +70 C | 0C to 70C (commercial) |
| Technology | CMOS EPROM (UV-erasable) | CMOS |
| Programming Method | JEDEC fuse-map / UV-erase | JEDEC fuse map, UV erasure |
| Speed Grade Suffix | -25 (25 ns tPD) | — |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Logic Expanders | — | 4 |
| Dedicated Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Propagation Delay (tPD) | — | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |