EP610DC-35 vs EP610DI-30N Comparison
Detailed side-by-side comparison of EP610DC-35 by Altera and EP610DI-30N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-35 | EP610DI-30N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 30 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V ±5% |
| Process Technology | CMOS | CMOS |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| Package | 24-pin CDIP (windowed CERDIP) 0.300 inch | CDIP-24 (Ceramic DIP, windowed) |
| Mounting Type | Through-Hole (DIP) | Through-hole (DIP) |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | -40°C to +85°C (industrial) |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| RoHS Status | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | [DATA_NEEDED: RoHS status] |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| Pin Count | — | 24 |
| Programming Method | — | UV-erasable (windowed ceramic) |
| MSL Level | — | [DATA_NEEDED: MSL level] |