EP610DC-35 vs EP610DI-30N Perbandingan
Perbandingan bersamaan detil EP610DC-35 dari Altera dan EP610DI-30N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP610DC-35 | EP610DI-30N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 30 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V ±5% |
| Process Technology | CMOS | CMOS |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| Paket | 24-pin CDIP (windowed CERDIP) 0.300 inch | CDIP-24 (Ceramic DIP, windowed) |
| Tipe Mounting | Through-Hole (DIP) | Through-hole (DIP) |
| Suhu Kerja | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | -40°C to +85°C (industrial) |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| Status RoHS | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | [DATA_NEEDED: RoHS status] |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| Jumlah Pin | — | 24 |
| Programming Method | — | UV-erasable (windowed ceramic) |
| Level MSL | — | [DATA_NEEDED: MSL level] |