EP610DI-30N vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610DI-30N by Altera and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DI-30N | EP610DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EP610 | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±5% | 5 V |
| Package | CDIP-24 (Ceramic DIP, windowed) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Pin Count | 24 | — |
| Operating Temperature | -40°C to +85°C (industrial) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Process Technology | CMOS | CMOS |
| Programming Method | UV-erasable (windowed ceramic) | — |
| Mounting Type | Through-hole (DIP) | Through-Hole (DIP) |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | — | CPLD - Classic EPLD |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |