EP610DI-30N vs EP610DC-35 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610DI-30N disebabkan oleh Altera dan EP610DC-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP610DI-30N | EP610DC-35 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EP610 | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±5% | 5 V |
| Kemasan | CDIP-24 (Ceramic DIP, windowed) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Kiraan Pin | 24 | — |
| Suhu Operasi | -40°C to +85°C (industrial) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Process Technology | CMOS | CMOS |
| Programming Method | UV-erasable (windowed ceramic) | — |
| Jenis Pemasangan | Through-hole (DIP) | Through-Hole (DIP) |
| Aras MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | — | CPLD - Classic EPLD |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |