EP610DI-30N vs EP610DC-35 Vergleich
Detaillierter Direktvergleich von EP610DI-30N von Altera und EP610DC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610DI-30N | EP610DC-35 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,80 | $18,40 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EP610 | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±5% | 5 V |
| Gehäuse | CDIP-24 (Ceramic DIP, windowed) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Pin-Anzahl | 24 | — |
| Betriebstemperatur | -40°C to +85°C (industrial) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Process Technology | CMOS | CMOS |
| Programming Method | UV-erasable (windowed ceramic) | — |
| Montageart | Through-hole (DIP) | Through-Hole (DIP) |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | — | CPLD - Classic EPLD |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |