EP610IDC-15 vs EP610ILI-12 Comparison
Detailed side-by-side comparison of EP610IDC-15 by Intel and EP610ILI-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IDC-15 | EP610ILI-12 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | NRND |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial grade) |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Package | 24-pin CerDIP (ceramic DIP) | 28-pin PLCC (J-Lead) |
| Mounting Type | Through-hole | Surface Mount |
| I/O Pins | 24 (per package; macrocell-programmable) | — |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS Status | [DATA_NEEDED: RoHS status of CerDIP variant] | [DATA_NEEDED: RoHS status] |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Family | — | Classic EPLD (EP610) |
| Macro Cells | — | 16 |
| Speed Grade (tpd) | — | 12 ns |
| Supply Voltage (Vcc) | — | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (Vpp) | — | [DATA_NEEDED: Vpp programming voltage] |
| Operating Frequency (max) | — | 83.3 MHz |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| User I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Dedicated Inputs | — | 4 |
| Technology | — | CMOS EPROM |
| Programmable Security Bit | — | Yes |
| TTL Compatibility | — | 100 TTL emulation |
| MSL Level | — | [DATA_NEEDED: MSL rating] |