EP610IDC-15 vs EP610ILI-12 比較
詳細並排比較 EP610IDC-15 由 Intel 與 EP610ILI-12 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610IDC-15 | EP610ILI-12 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | NRND |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作溫度 | 0C to +70C (commercial) | -40C to +85C (industrial grade) |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 封裝 | 24-pin CerDIP (ceramic DIP) | 28-pin PLCC (J-Lead) |
| 安裝類型 | Through-hole | Surface Mount |
| I/O Pins | 24 (per package; macrocell-programmable) | — |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of CerDIP variant] | [DATA_NEEDED: RoHS status] |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Family | — | Classic EPLD (EP610) |
| Macro Cells | — | 16 |
| Speed Grade (tpd) | — | 12 ns |
| Supply Voltage (Vcc) | — | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (Vpp) | — | [DATA_NEEDED: Vpp programming voltage] |
| Operating Frequency (max) | — | 83.3 MHz |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| User I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Dedicated Inputs | — | 4 |
| Technology | — | CMOS EPROM |
| Programmable Security Bit | — | Yes |
| TTL Compatibility | — | 100 TTL emulation |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |