EP610IDC-15 vs EP610LI-15 Comparison
Detailed side-by-side comparison of EP610IDC-15 by Intel and EP610LI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP610LI-15 - 16-Macrocell CMOS EPLD, 15ns tPD | Altera (Rochester)
EP610LI-15 ⚠ Last Time BuySpecification Comparison
| Parameter | EP610IDC-15 | EP610LI-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Last Time Buy |
| Device Family | Altera Classic EPLD | Classic EPLD EP610 |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 15 ns | 15 ns |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0C to +70C (commercial) | 0 C to +70 C (commercial, "I" grade) |
| Process Technology | CMOS, UV-erasable / OTP | CMOS EPROM (UV-erasable) |
| Package | 24-pin CerDIP (ceramic DIP) | 24-pin ceramic DIP, side-brazed, windowed (DIP-24) |
| Mounting Type | Through-hole | — |
| I/O Pins | 24 (per package; macrocell-programmable) | — |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS Status | [DATA_NEEDED: RoHS status of CerDIP variant] | Non-compliant (ceramic DIP, SnPb finish typical) |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Counter Frequency (fCNT) | — | 83.3 MHz |
| Pin Count | — | 24 |
| Programming Method | — | UV erase + EPROM programmer |
| Logic Blocks | — | AND/OR array, 16 output macrocells |
| I/O Standard | — | TTL/CMOS compatible |
| Output Type | — | 3-state |
| Manufacturer (current) | — | Rochester Electronics (authorized Altera legacy distributor) |
| MSL Level | — | [DATA_NEEDED: MSL level] |