EP610IDC-15 vs EP610LI-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610IDC-15 sa pamamagitan ng Intel at EP610LI-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610IDC-15 EP610LI-15
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Huling Pagbili
Device Family Altera Classic EPLD Classic EPLD EP610
Macrocells 16 16
Usable Gates 300 —
Propagation Delay (tPD) 15 ns 15 ns
Maximum Frequency 66 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V nominal)
Temperature na Operasyon 0C to +70C (commercial) 0 C to +70 C (commercial, "I" grade)
Process Technology CMOS, UV-erasable / OTP CMOS EPROM (UV-erasable)
Packhaging 24-pin CerDIP (ceramic DIP) 24-pin ceramic DIP, side-brazed, windowed (DIP-24)
Uri ng Pagpapasok Through-hole —
I/O Pins 24 (per package; macrocell-programmable) —
Logic-Block Architecture AND/OR macrocell array with programmable flip-flops —
Program/Erase UV-erasable, OTP-compatible —
Development Tool MAX+PLUS II —
Tindminan RoHS [DATA_NEEDED: RoHS status of CerDIP variant] Non-compliant (ceramic DIP, SnPb finish typical)
Programming Current 11.0 mA typical (per Classic family datasheet) —
Counter Frequency (fCNT) — 83.3 MHz
Bilang ng Pin — 24
Programming Method — UV erase + EPROM programmer
Logic Blocks — AND/OR array, 16 output macrocells
I/O Standard — TTL/CMOS compatible
Type ng Output — 3-state
Manufacturer (current) — Rochester Electronics (authorized Altera legacy distributor)
Level ng MSL — [DATA_NEEDED: MSL level]

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