EP610ILC-10 vs EP610IPC-25 Comparison
Detailed side-by-side comparison of EP610ILC-10 by Altera and EP610IPC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610ILC-10 | EP610IPC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | — |
| Architecture | PAL-type with macrocells | PAL-type, CMOS, Erasable |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Product Terms | 160 | 160 |
| I/O Pins | 16 | — |
| Dedicated Inputs | 4 | — |
| Supply Voltage | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Package | PLCC-28 (plastic J-lead chip carrier) | 24-pin PDIP (Plastic DIP) |
| Mounting Type | Surface Mount (PLCC socket or solder) | Through-Hole |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (Commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (contains Pb, PDIP package) |
| Family | — | Classic EPLD (EP610) |
| Propagation Delay (tpd) | — | 25 ns (max) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| Technology | — | CMOS, UV-erasable (windowless in IPC pkg) |
| TTL Compatibility | — | 100% TTL emulation |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| Logic Capacity | — | Equivalent to ~24 standard 24-pin PALs |