EP610ILC-10 vs EP610IPC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILC-10 sa pamamagitan ng Altera at EP610IPC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610ILC-10 | EP610IPC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | — |
| Architecture | PAL-type with macrocells | PAL-type, CMOS, Erasable |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Product Terms | 160 | 160 |
| I/O Pins | 16 | — |
| Dedicated Inputs | 4 | — |
| Volte ng Pagbibigay | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Packhaging | PLCC-28 (plastic J-lead chip carrier) | 24-pin PDIP (Plastic DIP) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or solder) | Through-Hole |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (Commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (contains Pb, PDIP package) |
| Family | — | Classic EPLD (EP610) |
| Propagation Delay (tpd) | — | 25 ns (max) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| Technology | — | CMOS, UV-erasable (windowless in IPC pkg) |
| TTL Compatibility | — | 100% TTL emulation |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Logic Capacity | — | Equivalent to ~24 standard 24-pin PALs |