EP610IPC-10 vs EP610DC-10 Comparison
Detailed side-by-side comparison of EP610IPC-10 by Altera and EP610DC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IPC-10 | EP610DC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $7.95 |
| Family | Altera Classic EPLD | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Programmable Gates | 300 usable gates | β |
| Macrocells | 16 | 16 |
| Maximum Operating Frequency | 100 MHz | β |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | β |
| Product Terms | 160 total | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 16 | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Total Input Pins | 20 | β |
| Supply Voltage | 5 V | 5 V (single supply) |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | β |
| Technology | CMOS EPROM (UV-erasable / OTP) | CMOS, EPROM-based (UV-erasable) |
| Package | 24-pin PDIP (Plastic DIP) | 24-pin CDIP (Ceramic DIP, windowed) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | β |
| TTL Emulation | 100% TTL compatible | β |
| Device Family | β | Altera Classic EPLD |
| Maximum Pipelined Data Rate | β | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | β | 10 ns |
| Speed Grade | β | -10 |
| Mounting Type | β | Through-Hole |
| Logic Elements | β | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | β | UV-erasable EPROM |
| Reprogrammable | β | Yes (UV erase window on package) |
| RoHS Status | β | [DATA_NEEDED: not stated in verified web data] |