EP610IPC-10 vs EP610DC-10 Vergleich
Detaillierter Direktvergleich von EP610IPC-10 von Altera und EP610DC-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610IPC-10 | EP610DC-10 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,40 | $7,95 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Programmable Gates | 300 usable gates | — |
| Macrocells | 16 | 16 |
| Maximum Operating Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | — |
| Product Terms | 160 total | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Total Input Pins | 20 | — |
| Versorgungsspannung | 5 V | 5 V (single supply) |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | — |
| Technology | CMOS EPROM (UV-erasable / OTP) | CMOS, EPROM-based (UV-erasable) |
| Gehäuse | 24-pin PDIP (Plastic DIP) | 24-pin CDIP (Ceramic DIP, windowed) |
| Betriebstemperatur | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | — |
| TTL Emulation | 100% TTL compatible | — |
| Device Family | — | Altera Classic EPLD |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| Montageart | — | Through-Hole |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |
| RoHS-Status | — | [DATA_NEEDED: not stated in verified web data] |