EP610IPC-10 vs EP610DC-10 对比
详细并排对比 EP610IPC-10 出自 Altera 和 EP610DC-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610IPC-10 | EP610DC-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.40 | $7.95 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Programmable Gates | 300 usable gates | — |
| Macrocells | 16 | 16 |
| Maximum Operating Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | — |
| Product Terms | 160 total | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Total Input Pins | 20 | — |
| 电源电压 | 5 V | 5 V (single supply) |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | — |
| Technology | CMOS EPROM (UV-erasable / OTP) | CMOS, EPROM-based (UV-erasable) |
| 封装 | 24-pin PDIP (Plastic DIP) | 24-pin CDIP (Ceramic DIP, windowed) |
| 工作温度 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | — |
| TTL Emulation | 100% TTL compatible | — |
| Device Family | — | Altera Classic EPLD |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| 安装类型 | — | Through-Hole |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |
| RoHS 状态 | — | [DATA_NEEDED: not stated in verified web data] |