EP610IPC-25 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610IPC-25 by Intel and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ ActiveSpecification Comparison
| Parameter | EP610IPC-25 | EP610DC-25 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Active |
| Family | Classic EPLD (EP610) | Altera Classic EPLD |
| Architecture | PAL-type, CMOS, Erasable | — |
| Propagation Delay (tpd) | 25 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | — |
| Operating Temperature | 0 °C to +70 °C (Commercial) | 0 C to +70 C |
| Package | 24-pin PDIP (Plastic DIP) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | CMOS EPROM (UV-erasable) |
| TTL Compatibility | 100% TTL emulation | — |
| Mounting Type | Through-Hole | Through Hole |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | Non-compliant (contains Pb, PDIP package) | — |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |