EP610IPC-25 vs EP610DC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610IPC-25 sa pamamagitan ng Intel at EP610DC-25 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP610IPC-25 | EP610DC-25 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Family | Classic EPLD (EP610) | Altera Classic EPLD |
| Architecture | PAL-type, CMOS, Erasable | — |
| Propagation Delay (tpd) | 25 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | — |
| Temperature na Operasyon | 0 °C to +70 °C (Commercial) | 0 C to +70 C |
| Packhaging | 24-pin PDIP (Plastic DIP) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | CMOS EPROM (UV-erasable) |
| TTL Compatibility | 100% TTL emulation | — |
| Uri ng Pagpapasok | Through-Hole | Through Hole |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Non-compliant (contains Pb, PDIP package) | — |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |