EP610LC-15 vs EP610LC-25 Comparison
Detailed side-by-side comparison of EP610LC-15 by Altera and EP610LC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-15 | EP610LC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD (EP610) | Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Equivalent Gates | 300 gates | — |
| Propagation Delay (tpd) | 15 ns | — |
| Counter Frequency (fmax) | 83.3 MHz | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (Vcc) | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Package | 28-pin PLCC (J-lead, plastic OTP) | PLCC-28 |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Pins | 28 | — |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] | 0C to +70C (commercial) |
| Programming | OTP (one-time programmable) | — |
| RoHS Status | unknown | [DATA_NEEDED] |
| MSL Level | [DATA_NEEDED: MSL rating] | — |
| Macrocells | — | 16 |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | 100 MHz |
| Supply Voltage | — | 5 V ±5% |
| Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed package) |
| I/O Pins | — | [DATA_NEEDED: exact I/O count] |