EP610LC-15 vs EP610LC-25 Vergleich
Detaillierter Direktvergleich von EP610LC-15 von Altera und EP610LC-25 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610LC-15 | EP610LC-25 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,65 | $6,20 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD (EP610) | Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Equivalent Gates | 300 gates | — |
| Propagation Delay (tpd) | 15 ns | — |
| Counter Frequency (fmax) | 83.3 MHz | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (Vcc) | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Gehäuse | 28-pin PLCC (J-lead, plastic OTP) | PLCC-28 |
| Montageart | Surface Mount | Surface Mount |
| Anzahl der Pins | 28 | — |
| Betriebstemperatur | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] | 0C to +70C (commercial) |
| Programming | OTP (one-time programmable) | — |
| RoHS-Status | unknown | [DATA_NEEDED] |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| Macrocells | — | 16 |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | 100 MHz |
| Versorgungsspannung | — | 5 V ±5% |
| Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed package) |
| I/O Pins | — | [DATA_NEEDED: exact I/O count] |