EP610LC-15 vs EP610LC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-15 sa pamamagitan ng Altera at EP610LC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610LC-15 | EP610LC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD (EP610) | Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Equivalent Gates | 300 gates | — |
| Propagation Delay (tpd) | 15 ns | — |
| Counter Frequency (fmax) | 83.3 MHz | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (Vcc) | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Packhaging | 28-pin PLCC (J-lead, plastic OTP) | PLCC-28 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Bilang ng Pins | 28 | — |
| Temperature na Operasyon | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] | 0C to +70C (commercial) |
| Programming | OTP (one-time programmable) | — |
| Tindminan RoHS | unknown | [DATA_NEEDED] |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Macrocells | — | 16 |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | 100 MHz |
| Volte ng Pagbibigay | — | 5 V ±5% |
| Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed package) |
| I/O Pins | — | [DATA_NEEDED: exact I/O count] |