EP610LC-30 vs EP610LC-15 Comparison
Detailed side-by-side comparison of EP610LC-30 by Intel and EP610LC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-30 | EP610LC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $4.65 |
| Family | Classic EPLD (EP610) | Altera Classic EPLD (EP610) |
| Macro Cells | 16 | β |
| Logic Gates | Equivalent to 300 gates (typical) | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Programming Voltage (VPP) | 13 V nominal | β |
| Technology | CMOS EPROM (UV-erasable) | β |
| Package | 24-pin CERDIP / PDIP | 28-pin PLCC (J-lead, plastic OTP) |
| Operating Temperature | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] |
| Erase/Program Cycles | 1000 typical | β |
| Mounting Type | Through-Hole | Surface Mount |
| Output Type | CMOS tri-state (programmable) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Logic Compatibility | TTL and CMOS | β |
| Turbo Mode | Yes (registered path bypass) | β |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Elements / Macrocells | β | 16 macrocells |
| Equivalent Gates | β | 300 gates |
| Propagation Delay (tpd) | β | 15 ns |
| Counter Frequency (fmax) | β | 83.3 MHz |
| Supply Voltage (Vcc) | β | 5 V (single supply) |
| Process Technology | β | CMOS |
| Number of Pins | β | 28 |
| Programming | β | OTP (one-time programmable) |
| MSL Level | β | [DATA_NEEDED: MSL rating] |