EP610LC-30 vs EP610LC-15 Vergleich
Detaillierter Direktvergleich von EP610LC-30 von Intel und EP610LC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610LC-30 | EP610LC-15 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,40 | $4,65 |
| Family | Classic EPLD (EP610) | Altera Classic EPLD (EP610) |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Gehäuse | 24-pin CERDIP / PDIP | 28-pin PLCC (J-lead, plastic OTP) |
| Betriebstemperatur | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] |
| Erase/Program Cycles | 1000 typical | — |
| Montageart | Through-Hole | Surface Mount |
| Ausgangstyp | CMOS tri-state (programmable) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Elements / Macrocells | — | 16 macrocells |
| Equivalent Gates | — | 300 gates |
| Propagation Delay (tpd) | — | 15 ns |
| Counter Frequency (fmax) | — | 83.3 MHz |
| Supply Voltage (Vcc) | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Anzahl der Pins | — | 28 |
| Programming | — | OTP (one-time programmable) |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |