EP610LC-30 vs EP610LC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-30 sa pamamagitan ng Intel at EP610LC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610LC-30 | EP610LC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD (EP610) | Altera Classic EPLD (EP610) |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Packhaging | 24-pin CERDIP / PDIP | 28-pin PLCC (J-lead, plastic OTP) |
| Temperature na Operasyon | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] |
| Erase/Program Cycles | 1000 typical | — |
| Uri ng Pagpapasok | Through-Hole | Surface Mount |
| Type ng Output | CMOS tri-state (programmable) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Elements / Macrocells | — | 16 macrocells |
| Equivalent Gates | — | 300 gates |
| Propagation Delay (tpd) | — | 15 ns |
| Counter Frequency (fmax) | — | 83.3 MHz |
| Supply Voltage (Vcc) | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Bilang ng Pins | — | 28 |
| Programming | — | OTP (one-time programmable) |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |