EP610LC-35 vs EP610LI-35 Comparison
Detailed side-by-side comparison of EP610LC-35 by Altera and EP610LI-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-35 | EP610LI-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Device Series | EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tpd) | 37 ns | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | — |
| Package | 28-pin PLCC (J-lead) | 28-pin PLCC (windowed ceramic, 'LI') |
| Operating Temperature | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | — |
| Speed Grade | -35 (slowest EP610) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| MSL Level | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Series | — | EP610 |
| Number of Macrocells | — | 16 |
| Number of I/O Pins | — | 16 |
| Total Inputs | — | 20 |
| Dedicated Inputs | — | 4 |
| External Clock Inputs | — | 2 |
| Product Terms | — | 160 |
| Maximum Propagation Delay | — | 35 ns (tpd) |
| Maximum Operating Frequency | — | 28.6 MHz (fmax) |
| Pipelined Data Rate | — | Up to 100 MHz |
| Supply Voltage | — | 5 V |
| Process Technology | — | CMOS |
| Architecture | — | PAL-type (AND-OR array) |
| Operating Temperature Range | — | [DATA_NEEDED: military/industrial operating temperature range] |
| Programming Technology | — | UV-erasable (EPROM) |