EP610LC-35 vs EP610LI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-35 sa pamamagitan ng Altera at EP610LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610LC-35 | EP610LI-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Device Series | EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tpd) | 37 ns | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | — |
| Packhaging | 28-pin PLCC (J-lead) | 28-pin PLCC (windowed ceramic, 'LI') |
| Temperature na Operasyon | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | — |
| Speed Grade | -35 (slowest EP610) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| Level ng MSL | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Series | — | EP610 |
| Number of Macrocells | — | 16 |
| Number of I/O Pins | — | 16 |
| Total Inputs | — | 20 |
| Dedicated Inputs | — | 4 |
| External Clock Inputs | — | 2 |
| Product Terms | — | 160 |
| Maximum Propagation Delay | — | 35 ns (tpd) |
| Maximum Operating Frequency | — | 28.6 MHz (fmax) |
| Pipelined Data Rate | — | Up to 100 MHz |
| Volte ng Pagbibigay | — | 5 V |
| Process Technology | — | CMOS |
| Architecture | — | PAL-type (AND-OR array) |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: military/industrial operating temperature range] |
| Programming Technology | — | UV-erasable (EPROM) |