EP610PC-15 vs EP610PC-25 Comparison
Detailed side-by-side comparison of EP610PC-15 by Altera and EP610PC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-15 | EP610PC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.50 | $9.75 |
| Family | Classic EPLD | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | OT PLD, PAL-type, CMOS |
| Usable Gates | 300 gates | 300 |
| Macrocells | 16 | β |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | β |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | β |
| Pipelined Data Rate | Up to 100 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | β |
| Technology | CMOS | CMOS, EPROM (UV-erasable) |
| Architecture | PAL-type, sum-of-products AND/OR array | β |
| TTL Emulation | 100% TTL compatible | β |
| Package | PDIP-24 (plastic DIP, 24-pin) | PDIP-24 (0.3 inch, through-hole) |
| Pin Count | 24 pins | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| Mounting Type | Through-Hole (DIP) | Through-Hole (DIP) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Development Tool | Altera MAX+PLUS II | β |
| Logic Test Circuitry | On-board for AC/DC verification | β |
| Device Family | β | Classic EPLD (EP610 series) |
| Macro Cells | β | 16 |
| Propagation Delay (tpd) | β | 25 ns |
| Maximum Pipelined Data Rate | β | 100 MHz |
| Supply Voltage (Vcc) | β | 5 V (nominal) |
| Dedicated Inputs | β | 4 |
| I/O Pins | β | 20 (bidirectional, JTAG-programmable OE per macrocell) |
| Programming Method | β | EPROM (UV-erasable), via Altera programming hardware |