EP610PC-15 vs EP610PC-25 Comparação
Comparação detalhada lado a lado de EP610PC-15 por Altera e EP610PC-25 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP610PC-15 | EP610PC-25 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $17,50 | $9,75 |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | OT PLD, PAL-type, CMOS |
| Usable Gates | 300 gates | 300 |
| Macrocells | 16 | — |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS | CMOS, EPROM (UV-erasable) |
| Architecture | PAL-type, sum-of-products AND/OR array | — |
| TTL Emulation | 100% TTL compatible | — |
| Encapsulamento | PDIP-24 (plastic DIP, 24-pin) | PDIP-24 (0.3 inch, through-hole) |
| Contagem de pinos | 24 pins | — |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| Tipo de montagem | Through-Hole (DIP) | Through-Hole (DIP) |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Development Tool | Altera MAX+PLUS II | — |
| Logic Test Circuitry | On-board for AC/DC verification | — |
| Device Family | — | Classic EPLD (EP610 series) |
| Macro Cells | — | 16 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 20 (bidirectional, JTAG-programmable OE per macrocell) |
| Programming Method | — | EPROM (UV-erasable), via Altera programming hardware |