EP610PC-15 vs EP610PC-25 Comparaison
Comparaison détaillée côte à côte de EP610PC-15 par Altera et EP610PC-25 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610PC-15 | EP610PC-25 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,50 | $9,75 |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | OT PLD, PAL-type, CMOS |
| Usable Gates | 300 gates | 300 |
| Macrocells | 16 | — |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS | CMOS, EPROM (UV-erasable) |
| Architecture | PAL-type, sum-of-products AND/OR array | — |
| TTL Emulation | 100% TTL compatible | — |
| Boîtier | PDIP-24 (plastic DIP, 24-pin) | PDIP-24 (0.3 inch, through-hole) |
| Nombre de broches | 24 pins | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| Type de montage | Through-Hole (DIP) | Through-Hole (DIP) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Development Tool | Altera MAX+PLUS II | — |
| Logic Test Circuitry | On-board for AC/DC verification | — |
| Device Family | — | Classic EPLD (EP610 series) |
| Macro Cells | — | 16 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 20 (bidirectional, JTAG-programmable OE per macrocell) |
| Programming Method | — | EPROM (UV-erasable), via Altera programming hardware |