EP610PC-25 vs EP610PC-25T Comparison

Detailed side-by-side comparison of EP610PC-25 by Altera and EP610PC-25T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610PC-25 EP610PC-25T
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Device Family Classic EPLD (EP610 series) Altera Classic EPLD - EP610
Macro Cells 16 16
Usable Gates 300 —
Propagation Delay (tpd) 25 ns —
Maximum Pipelined Data Rate 100 MHz —
Supply Voltage (Vcc) 5 V (nominal) —
Technology CMOS, EPROM (UV-erasable) —
Device Type OT PLD, PAL-type, CMOS Erasable Programmable Logic Device (EPLD, OTP for plastic package)
Dedicated Inputs 4 —
I/O Pins 20 (bidirectional, JTAG-programmable OE per macrocell) —
Package PDIP-24 (0.3 inch, through-hole) PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing)
Operating Temperature [DATA_NEEDED: operating temperature grade] 0 °C to +70 °C (commercial)
Programming Method EPROM (UV-erasable), via Altera programming hardware OTP (one-time programmable) via Altera programming hardware
Mounting Type Through-Hole (DIP) Through-hole
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Manufacturer — Intel (formerly Altera)
Distributor / Stocking Source — Rochester Electronics, LLC
Logic Capacity — 300 usable gates
Registers — 16
User I/Os — 16
Propagation Delay (tPD) — 25 ns (speed grade 25)
Maximum Toggle Frequency — [DATA_NEEDED: max fmax]
Pipelined Data Rate — up to 100 MHz
Supply Voltage (VCC) — 5 V
Process Technology — ECMOS (CMOS, EPROM-based)
Pinout Compatibility — Pin-compatible with EP610DC-25 (CERDIP-24, windowed)
Shipping Form (T suffix) — Tube

Datasheets & Resources

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