EP610PC-25 vs EP610PC-25T 比較

詳細並排比較 EP610PC-25 由 Altera 與 EP610PC-25T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP610PC-25 EP610PC-25T
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 最後購買
Device Family Classic EPLD (EP610 series) Altera Classic EPLD - EP610
Macro Cells 16 16
Usable Gates 300 —
Propagation Delay (tpd) 25 ns —
Maximum Pipelined Data Rate 100 MHz —
Supply Voltage (Vcc) 5 V (nominal) —
Technology CMOS, EPROM (UV-erasable) —
Device Type OT PLD, PAL-type, CMOS Erasable Programmable Logic Device (EPLD, OTP for plastic package)
Dedicated Inputs 4 —
I/O Pins 20 (bidirectional, JTAG-programmable OE per macrocell) —
封裝 PDIP-24 (0.3 inch, through-hole) PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing)
工作溫度 [DATA_NEEDED: operating temperature grade] 0 °C to +70 °C (commercial)
Programming Method EPROM (UV-erasable), via Altera programming hardware OTP (one-time programmable) via Altera programming hardware
安裝類型 Through-Hole (DIP) Through-hole
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Manufacturer — Intel (formerly Altera)
Distributor / Stocking Source — Rochester Electronics, LLC
Logic Capacity — 300 usable gates
Registers — 16
User I/Os — 16
Propagation Delay (tPD) — 25 ns (speed grade 25)
Maximum Toggle Frequency — [DATA_NEEDED: max fmax]
Pipelined Data Rate — up to 100 MHz
Supply Voltage (VCC) — 5 V
Process Technology — ECMOS (CMOS, EPROM-based)
Pinout Compatibility — Pin-compatible with EP610DC-25 (CERDIP-24, windowed)
Shipping Form (T suffix) — Tube

資料表與資源

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