EP610PC-25 vs EP610PC-25T 比較
詳細な並列比較: EP610PC-25 メーカー: Altera および EP610PC-25T メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ ラストタイムバイ仕様比較
| パラメータ | EP610PC-25 | EP610PC-25T |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $28.95 |
| Device Family | Classic EPLD (EP610 series) | Altera Classic EPLD - EP610 |
| Macro Cells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 25 ns | — |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Technology | CMOS, EPROM (UV-erasable) | — |
| Device Type | OT PLD, PAL-type, CMOS | Erasable Programmable Logic Device (EPLD, OTP for plastic package) |
| Dedicated Inputs | 4 | — |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) | — |
| パッケージ | PDIP-24 (0.3 inch, through-hole) | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) |
| 動作温度 | [DATA_NEEDED: operating temperature grade] | 0 °C to +70 °C (commercial) |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware | OTP (one-time programmable) via Altera programming hardware |
| 実装タイプ | Through-Hole (DIP) | Through-hole |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Intel (formerly Altera) |
| Distributor / Stocking Source | — | Rochester Electronics, LLC |
| Logic Capacity | — | 300 usable gates |
| Registers | — | 16 |
| User I/Os | — | 16 |
| Propagation Delay (tPD) | — | 25 ns (speed grade 25) |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fmax] |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | ECMOS (CMOS, EPROM-based) |
| Pinout Compatibility | — | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) |
| Shipping Form (T suffix) | — | Tube |