EP610PC-25 vs EP910PC-35 Comparison
Detailed side-by-side comparison of EP610PC-25 by Altera and EP910PC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-25 | EP910PC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP610 series) | — |
| Macro Cells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 25 ns | — |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Technology | CMOS, EPROM (UV-erasable) | CMOS, UV-erasable/OTP |
| Device Type | OT PLD, PAL-type, CMOS | EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | 4 | 12 |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) | 24 |
| Package | PDIP-24 (0.3 inch, through-hole) | 40-pin PDIP (Plastic DIP) |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature range] |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| Family | — | Classic EPLD |
| Macrocells | — | 24 |
| Total Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Counter Frequency | — | 37 MHz |
| Internal Performance Frequency | — | 100 MHz |
| Supply Voltage | — | 5 V |
| Architecture | — | PAL-type sum-of-products, AND/OR array |
| Compliance / RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |